Recently, electric double-layer capacitors (EDLCs) have attracted an attention as new electric power storage device to take a place of secondary batteries due to the features such as a long cycle life and a wide working-temperature range. However, capacitors vary in output voltage in proportion to the electric charge stored, and the output voltage is low when using a single capacitor. Accordingly, it is common to use such capacitors by connecting more than one capacitor in series or in serial-parallel.
A known method in order to supply a stable voltage to a load when capacitors are connected in series or in serial-parallel is such that a plurality of EDLCs are switched between series and serial-parallel using complex switches.
In an electric power storage system constituted from a plurality of EDLCs connected in serial-parallel, in order to improve the charging/discharging efficiency, two control techniques called “bank switching” and “voltage equalizing circuit” are usually used at the same time. The following outlines these control techniques, and describes problems arising when these techniques are used in conjunction.
[Bank Switching]
The conventionally proposed technique of “bank switching” (for example, refer to Japanese Patent Laid-Open No. 11-215695) is to control a plurality of switches that are arranged along with a plurality of EDLCs in multiple stages as shown in FIG. 1A, thereby switching connection states of EDLCs sequentially as shown in FIGS. 1B, 1C and 1D. In the following description, a group of capacitors constituting one stage is called a “block”. Further, each capacitor illustrated in the drawings may be constituted by more than one capacitor connected in serial-parallel.
In a discharging process, for example, of a conventional electric power storage system as shown in FIG. 1, every time an output voltage of the electric power storage system falls and becomes close to a minimum input voltage of an inverter as the voltage of each capacitor (EDLC) decreases due to the discharge, a connection among EDLCs in a block in which the EDLCs are connected in parallel is switched to a serial connection sequentially block by block in an order of FIGS. 1A, 1B, and 1C. By this, the output voltage of the electric power storage system is controlled so as to fall into an input range of the inverter, and the electric power storage system outputs the electric power until all the EDLCs are finally connected in series as shown in FIG. 1D. It is noted that EDLCs of a block in which EDLCs have been switched to the serial connection are not switched back to the parallel connection.
Further, in a charging process, every time the output voltage of the electric power storage system rises and becomes close to a maximum input voltage of an inverter as the voltage of each capacitor (EDLC) increases, the connection among EDLCs in a block in which the EDLCs are connected in series is switched to the parallel connection sequentially block by block in a reverse order of the order in the discharging process. It is noted that EDLCs of a block in which EDLCs have been switched to the parallel connection are not switched back to the serial connection.
While the above described conventional “bank switching” technique is effective in improving charging/discharging characteristics or depth of discharge, the following problems have been noted.
(1) Variation in Inter-Terminal Voltages Between Blocks
In the charging process, for example, because the amount of charge accumulated in each EDLC in a block in which EDLCs are connected in parallel becomes half the amount of charge accumulated in each EDLC of a block having EDLCs connected in series, when the EDLCs connected in series in a block in which EDLCs are switched to a parallel connection, a variation in EDLC inter-terminal voltage between the blocks is caused. When a variation in EDLC inter-terminal voltage is caused, the EDLCs in the block in which the EDLCs are connected in series are overcharged unless the inter-terminal voltages of the EDLCs in the block in which the EDLCs are connected in series are maintained to be equal to or lower than than the withstand voltage until the EDLCs in the block having EDLCs switched to a parallel connection are fully charged.
(2) Difference in Charging Characteristics Due to a Difference in the Numbers of EDLCs Constituting Blocks
Generally, the system should be constructed so that the number of EDLCs constituting each block is identical. However, in some cases, the number of EDLCs in each block becomes unavoidably different. In such a case, in the charging process, when the connection of the EDLCs of a block having the larger number of EDLCs is switched from series to parallel, the output voltage Vt of the electric power storage system decreases extremely and a large amount of time may thus be required until the EDLCs that have been switched to parallel are charged and the subsequent switching occurs. In the worst case, the output voltage Vt of the electric power storage system may fall below the inverter input voltage range.
Moreover, even if the output voltage Vt of the electric power storage system does not fall below the inverter input voltage range, the EDLC inter-terminal voltages of the blocks becomes largely varied, and consequently, the voltages of the EDLCs which have been fully charged may exceeds withstand voltage the as the charging proceeds, thereby causing breakdown.
(3) Laterally Flowing Current
As shown in FIG. 2, in a charging process, when the connection of EDLCs in a block is switched from a serial connection as shown in FIG. 2A to a parallel connection as shown in FIG. 2B, if there is a variation between inter-terminal voltage V1 of a capacitor (EDLC) C1 and inter-terminal voltage V2 of a capacitor (EDLC) C2, a laterally flowing current is generated. Therefore, in a case in which a semiconductor switch is used as the switch in FIG. 2, the laterally flowing current generated is expressed as (V2−V1)/R [A], where an ON resistance of the semiconductor switch is R [Ω], and this could destroy the semiconductor switch.
To prevent the laterally flowing current from being generated, it is necessary to suppress the variation in the inter-terminal voltages of EDLCs that are connected in parallel.
With the above described problems, it is difficult to construct an electric power storage system by using only “bank switching”. However, these problems can be avoided by taking the following measures.
(1) Add a control circuit which prevents the inter-terminal voltage of the EDLCs from exceeding the withstand voltage.
(2) Add a control circuit which suppresses a variation in inter-terminal voltage of the EDLCs at all times.
(3) Make the number of EDLCs constituting each block as identical as possible.
In order to realize the above (1) and (2), a circuit called “voltage equalizing circuit” is used.
[Voltage Equalizing Circuit]
The voltage equalizing circuit is a control circuit which suppresses a variation in the inter-terminal voltage of each EDLC and serves to improve the safety of an electric power storage system.
In an electric power storage system based on the bank switching, factors of generation of a variation in the EDLC inter-terminal voltages include “difference of capacitance of each EDLC”, “difference in self-discharge characteristics of each EDLC” and “difference in the amount of charge flowing to each EDLC caused by the bank switching”. When these multiple factors are combined, the above described three problems arise: (1) A variation in inter-terminal voltage between blocks, (2) Difference in charging characteristics due to a difference in the numbers of EDLCs constituting blocks, and (3) A large laterally flowing current. Suppressing the EDLC inter-terminal voltage by a “voltage equalizing circuit” will be described below.
(1) Prevention of Overcharge
Prevention of overcharging of an EDLC by the voltage equalizing circuit is realized by arranging a resistor and a switch between the terminals of each EDLC. Specifically, the inter-terminal voltage of each EDLC is monitored and the switch connected to an EDLC in which the withstand voltage is about to be exceeded, is turned on, thereby discharging forcibly, and preventing the overcharge. By using the voltage equalizing circuit, the inter-terminal voltage of an EDLC which has reached the fully charged state faster than the other EDLCs, is kept equal to or smaller than the withstand voltage, whereby charging can be safely performed without overcharging. Adjusting the inter-terminal voltage of all the EDLCs to the same value as much as possible in this way is hereinafter referred to as “voltage equalization”. In addition, a loss caused by keeping the EDLC inter-terminal voltage equal to or smaller than the withstand voltage is referred to as “voltage equalization loss”.
(2) Prevention of Variation in Inter-Terminal Voltages of Capacitors (EDLCs)
The voltage equalizing circuit is also used to suppress the variation in the EDLC inter-terminal voltages. In a conventional manner, voltage equalization (“initialization” in Japanese Patent Laid-Open No. 2003-111286) for reducing the variation in inter-terminal voltages of capacitors is performed only around at a voltage for serial-parallel switching (refer to Japanese Patent Laid-Open No. 2003-111286, for example). In this way, by using the “voltage equalizing circuit” in conjunction with the “bank switching”, the “bank switching” can be safely performed to repeat charging and discharging of the EDLCs.
However, in the conventional electric power storage systems described above, the following problems arise when “bank switching” and “voltage equalizing circuit” are used in conjunction.
Actual EDLCs have errors in capacitances. Consequently, in the “conventional bank switching system” in which the connection state can be switched only in a predetermined block order, the following problems arise due to the errors in the total capacitances of the blocks.
Two blocks being in a parallel connection state in a charging process are taken as an example. When a total capacitance of one block is larger than that of the other block, it takes longer for the block with the larger total capacitance to be fully charged. In contrast, it takes shorter for the block with the smaller total capacitance to be fully charged. Consequently, until the block with the larger total capacitance is fully charged, the inter-terminal voltage of EDLC in the block with the smaller total capacitance must be kept equal to or smaller than the withstand voltage. Thus, the time period for overcharging prevention by the “voltage equalizing circuit” becomes longer and forced discharging is uselessly performed, causing a problem of increasing the voltage equalization loss.
Also, when there is only one EDLC having a smaller capacitance within each block, the variation in inter-terminal voltage of other EDLCs belonging to this same block is suppressed based on the inter-terminal voltage of the one EDLC. Accordingly, forced discharging is uselessly performed, causing a problem of deteriorating the charging/discharging characteristics.
Further, in the conventional manner, the voltage equalization (“initialization” in No. 2003-111286) for reducing the variation in inter-terminal voltages of capacitors is performed only around at a voltage for serial-parallel switching in order to prevent the variation in the EDLC inter-terminal voltages. However, when the variation in the inter-terminal voltages is excessively large at the time when the voltage equalization is performed, it takes longer to equalize the voltages, thereby causing a problem of increasing the voltage equalization loss.
One method to solve the above problems is to use EDLCs whose errors in capacitances are small. However, it is not practical to collect EDLCs having a similar capacitance and construct a system, because this leads to the waste of time for measuring capacitance and to an increase in the cost. Particularly, it takes a considerable time to accurately measure the capacitances of large-capacitance EDLCs to be used to construct an electric power storage system with a large-capacitance.